The present invention relates to a semiconductor integrated circuit which drops a voltage received from an external power supply before application of the voltage to an internal circuit.
Precision processing technologies have advanced with each new generation of semiconductor integrated circuit, enabling to reduce transistor size and to increase sensitivity. With this increased sensitivity and reduced transistor size, the current flowing through transistor channels produces hot electrons which can degrade the transistor. The voltage applied to the transistors can be reduced to prevent these hot electrons, but it is not possible to lower the voltage applied to by the external power supply (hereinafter applied external voltage) due to problems which would then be caused in assuring the operation of the overall system. As a result, the applied external voltage has conventionally been lowered inside the semiconductor integrated circuit before applying the voltage to the internal circuits (component parts, including the transistors).
In a conventional semiconductor integrated circuit as shown in FIG. 5, resistance R11, and n-channel transistors NT11, NT12, and NT13 are connected in sequence between the external power supply (applied external voltage Vex) and the ground, and the sum of the threshold voltages Vth of the n-channel transistors NT11, NT12, and NT13 is extracted as the reference voltage Vref from the connection of resistance R11 and n-channel transistor NT11. It is to be noted that the gates of the n-channel transistors NT11, NT12, and NT13 are each connected to the power supply side terminal of each transistor. Note also that a p-channel transistor PT11 is connected between the external power supply and the internal circuit Z. The reference voltage Vref is the input to the inversion terminal of the differential amplifier OP11, the internal voltage Vint occurring at the connection T11 between the p-channel transistor PT11 and the internal circuit Z is the non-inversion input of the differential amplifier OPII, and the differential amplifier OP11 controls the conductance of the p-channel transistor PT11 so that the potential difference (Vint - Vref) is approximately zero. In other words, a voltage drop circuit 10 is formed from the differential amplifier OP11 and p-channel transistor PT11, and this voltage drop circuit 10 generates an internal voltage Vint of a degree approximately equal to the reference voltage Vref, i.e., the sum of the threshold voltages Vth of the n-channel transistors NT11, NT12, and NT13, irrespective of the level of the applied external voltage Vex and the internal circuit Z.
However, the qualitative requirements placed on semiconductor integrated circuits today are extremely high, and major components such as transistors must be aged at a high temperature and high voltage to eliminate any latent defects. However, because conventional semiconductor integrated circuits as described above drop the applied external voltage Vex to an approximately constant internal voltage Vint, a high voltage cannot be applied to the internal circuits by raising the value of the applied external voltage Vex.
In addition, when the applied external voltage Vex is applied directly to the internal circuit the transistor life is shortened as described above.